Hello Dhall people!
Software on RISC-V needs a way to discover the capabilities of the processor it runs on.
To define everything about that configuration, a task group was formed.
We’re currently discussing about which language to use for specifying the configuration in a human readable format. This configuration will then be translated to a binary representation and put in the flash of the processor, where probably firmware or an OS reads it from.
YAML was proposed as it’s used for a similar purpose on RISC-V already and people are familiar with it.
However, what is also important to us, is that the config can be validated using a schema and that it is written without too much duplication.
Since I’m a Haskell and Nix user, I was aware of Dhall and thought that it might be worth looking at.
At first I was skeptical and thought it might be too difficult for most people to use and read.
However, I have refactored my example configuration and now it’s very readable and offers a lot of advantages over other languages.
You can see the example here.
Yes, it is explicitly not formatted with
dhall lint because the it’s quite unreadable to the untrained eye.
To summarize what the config shows: We’re specifying the configuration for harts (hardware thread) and the uncore/non-core stuff of the processor.
You can find the discussions here: [link in next post]. They are readable to the public but in order to post, you need to be a member of the RISC-V foundation.
I presented my findings in the bi-weekly call this week and I’m posting theme to this thread.
I don’t have any immediate questions but I’d love to hear your opinion.
If you’re interested, it would be awesome if someone could check out the discussion on the task group and let me know what you think.